Metal-oxide-semiconductor or MOS ROM's have been traditionally manufactured, in P-channel form, by selectively thinning the oxide at the locations of potential MOS transistors in the manner set forth in U.S. Pat. No. 3,541,543, issued Nov. 11, 1970, to Crawford, assigned to Texas Instruments. The technique has proved very useful in large volume low-cost manufacture of ROM's because all of the process steps and masks, except one, are exactly the same regardless of the code programmed into the individual ROM. The gate level mask is the only mask which is unique to a given code.
It has become increasingly necessary to employ N-channel silicon gate MOS devices in memory and logic systems because of the advantage in operation speed or access time. However, the coding technique of U.S. Pat. No. 3,541,543 is not appropriate for use in the N-channel manufacturing process because the process steps are quite different from the P-channel process.
It is therefore an object of this invention to provide improved N-channel silicon gate ROM devices and method of manufacture thereof. Another object is to provide a method of programming ROM devices in a manner compatible with N-channel silicon gate processing. An additional object is to provide a method of programming N-channel silicon gate ROM devices wherein a minimum of mask changes is needed.